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ST72141
8-BIT MCU WITH 8K ROM/OTP/EPROM, 256 BYTES RAM, ELECTRIC-MOTOR CONTROL, ADC, WDG, SPI AND 2 TIMERS
PRODUCT OVERVIEW
s
s
s s s s
s s
s
s s s s s s s s
s
User Program Memory (ROM/OTP/EPROM): 8K bytes Data RAM: 256 bytes including 64 bytes of stack Master Reset and Power-On Reset Run and Power Saving modes Low Voltage Detector (LVD) Reset 14 multifunctional bidirectional I/O lines: - 14 interrupt inputs on 2 independent lines - 8 analog alternate inputs - 3 high sink outputs - 13 alternate functions - EMI filtering Software or Hardware Watchdog (WDG) Motor Control peripheral featuring: - 6 PWM output channels - Emergency pin to force outputs to HiZ state - 3 analog inputs for rotor position detection with no need of additional sensors - Comparator for current control or limitation Two 16-bit Timers, each featuring: - 2 Input Captures - 2 Output Compares - External Clock input - PWM and Pulse Generator modes Synchronous Serial Peripheral Interface (SPI) 8-bit ADC with 8 channels 8-bit Data Manipulation 63 basic Instructions 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Complete Development Support on DOS/ WINDOWSTM Real-Time Emulator TM Full Software Package on DOS/WINDOWS (C-Compiler, Cross-Assembler, Debugger)
PSDIP32
CSDIP32W
SO34
Device Summary
Features Program Memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Temperature Range Package ST72141K2 8K 256 (64) MotorControl, Watchdog, Timers, SPI, ADC 4.5 to 5.5 V 8 or 4 MHz (16 or 8MHz oscillator) - 40C to + 85C SO34 - PSDIP32
Rev. 1.1
July 1998
This is preliminary information on a newproduct in development or undergoing evaluation. Details are subject to change without notice.
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ST72141
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST72141 Microcontroller Unit (MCU) is a member of the ST7 family of Microcontrollers. The device is based on an industry-standard 8-bit core and features an enhanced instruction set. The device is operated at an 8 or 16MHz oscillator frequency. Under software control, the ST72141 may be placed in either Wait, Slow or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8bit data management, the ST72141 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The device includes a low consumption and fast start on-chip oscillator, Figure 1. ST72E14 Block Diagram CPU, ROM/OTP/EPROM, RAM, 14 I/O lines and the following on-chip peripherals: Analog-to-Digital converter (ADC) with 8 multiplexed analog inputs, Motor Control (MTC) peripheral, industry standard synchronous SPI serial interface, digital Watchdog, two independent 16-bit Timers featuring Clock Inputs, Pulse Generator capabilities, 2 Input Captures and 2 Output Compares. The MTC peripheral is designed to control electric brushless motors, with or without sensors. An example of application is givenFigure 2 for 6-step control of Permanent Magnet Direct Current (PMDC) motor.
OSCIN OSCOUT VDD VSS RESET
Internal CLOCK OSC DIV
PORT A 8-BIT ADC PA7-PA0 (8 bits) OC1A
POWER SUPPLY
LVD
ADDRESS AND DATA BUS
TIMER B TIMER A
CONTROL
MCO5-MCO0 MCIA-C MOTOR CTRL MCES MICCFI PORT B SPI PB5-PB0 (6 bits)
8-BIT CORE ALU
Program Memory 8KBytes
RAM 256 Bytes
WATCHDO G
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Figure 2. Example of a 6-step-controlled Motor
ST7 MTC
MCO5-0 6 T0 T2
300V
T4
MCIB
B I1 I4 I3 I5
T3 T5
I6
MCIA MCIC MCCFI
A I2
C
T1
Current feedback
Step Switch T0 T1 T2 T3 T4 T5 Node A B C
300V 150V 0 300V 150V 0 300V 150V 0
1
2
3
4
5
6
1
2
3
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1.2 PIN DESCRIPTION Figure 3. 34-Pin SO Package Pinout
MCO5 MCO4 MCO3 MCO2 MCO1 MCO0 MCES MISO / EI2 / PB5 NC MOSI / EI2 / PB4 SCK/ EI2 / PB3 SS/ EI2 / PB2 EXTCLK_B/ EI2 / PB1 EXTCLK_A/ EI2 / PB0 OSCIN OSCOUT RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
MCIA MCIB MCIC MCCFI VD D VSS TEST/VPP OCP1A NC PA7 / AIN7 / EI1 / OCP2A PA6 / AIN6 / EI1 / ICP1A PA5 / AIN5 / EI1/ ICP2A PA4 / AIN4 / EI1/ OCP1B PA3 / AIN3 / EI1/ OCP2B PA2 / AIN2 / EI1/ ICP1B PA1 / AIN1 / EI1/ ICP2B PA0 / AIN0 / EI1
Factory fixed Open Drain (Push-Pull programming not available) - High Sink
Figure 4. 32-Pin SDIP Package Pinout
MCO5 MCO4 MCO3 MCO2 MCO1 MCO0 MCES MISO / EI2 / PB5 MOSI / EI2 / PB4 SCK/ EI2 / PB3 SS/ EI2 / PB2 EXTCLK_B/ EI2 / PB1 EXTCLK_A/ EI2 / PB0 OSCIN OSCOUT RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 MCIA MCIB MCIC MCCFI VDD VSS TEST/V PP OCP1A PA7 / AIN7 / EI1 / OCP2A PA6 / AIN6 / EI1 / ICP1A PA5 / AIN5 / EI1/ ICP2A PA4 / AIN4 / EI1/ OCP1B PA3 / AIN3 / EI1/ OCP2B PA2 / AIN2 / EI1/ ICP1B PA1 / AIN1 / EI1/ ICP2B PA0 / AIN0 / EI1
Factory fixe d Open Drain (Push-Pull programming not available) - High Sink
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Table 1. ST72E141 Pin Description
Pin n Pin n SO34 SDIP32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 25 26 27 28 29 30 31 32 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8
Levels Pin Name
MCO5 MCO4 MCO3 MCO2 MCO1 MCO0 MCES MISO/EI2/PB5 NC MOSI/EI2/PB4 SCK/EI2/PB3 SS/EI2/PB2 EXTCLK_B/EI2/PB1 EXTCLK_A/EI2/PB0 OSCIN OSCOUT RESET PA0/AIN0/EI1 PA1/AIN1/EI1/ ICP2B PA2/AIN2/EI1/ ICP1B PA3/AIN3/EI1/ OCP2B PA4/AIN4/EI1/ OCP1B PA5/AIN5/EI1/ ICP2A PA6/AIN6/EI1/ ICP1A PA7/AIN7/EI1/ OCP2A NC OCP1A TEST/VPP1) VSS VDD MCCFI MCIC MCIB MCIA O I/S S S I I I I A A A A R I/O O I/O I/O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O C C/A C/A C/A C/A C/A C/A C/A C/A C C C C C C C C C C C C C C C C C C C
Type In
O O O O O O I I/O C C C
Description Out
C C C C C C MTC Output Channel 5 MTC Output Channel 4 MTC Output Channel 3 MTC Output Channel 2 MTC Output Channel 1 MTC Output Channel 0 MTC Emergency Stop Port B5 or SPI Master In / Slave Out Data Not Connected Port B4 or SPI Master Out / Slave In Data Port B3 or SPI Serial Clock Port B2 or SPI Slave Select (active low) Port B1 or Timer B Input Clock Port B0 or Timer A Input Clock
Remarks
External Interrupt: EI2 External Interrupt: EI2 External Interrupt: EI2 Ext. Int.: EI2, High Sink Ext. Int.: EI2, High Sink Ext. Int.: EI2, High Sink
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. Bidirectional. Active low. Top priority non maskable interrupt. Port A0 or ADC Analog Input 0 External Interrupt: EI1 Port A1 or TimerB Input Capture 2 or ADC External Interrupt: EI1 Analog Input 1 Port A2 or TimerB Input Capture 1 or ADC External Interrupt: EI1 Analog Input 2 Port A3 or TimerB Output Compare 2 or ADC Analog Input 3 Port A4 or TimerB Output Compare 1 or ADC Analog Input 4 External Interrupt: EI1 External Interrupt: EI1
Port A5 or TimerA Input Capture 2 or ADC External Interrupt: EI1 Analog Input 5 Port A6 or TimerA Input Capture 1 or ADC External Interrupt: EI1 Analog Input 6 Port A7 or TimerA Output Compare 2 or ADC Analog Input 7 Not Connected TimerA Output Compare 1 Test mode pin (should be tied low in user mode). In the EPROM programming mode, this pin acts as the programming voltage input VPP Ground Main power supply MTC Current Feed Back MTC Input C MTC Input B MTC Input A External Interrupt: EI1
Note 1: V PP on EPROM/OTP only. - C = CMOS levels (0.3VDD / 0.7V DD) - R = 70k/100k Ratio of CMOS Levels (0.2V DD / 0.5VDD) - A = Analog levels
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1.3 MEMORY MAP Figure 5. Program Memory Map
0000h
HW Registers (see Table 3)
007Fh 0080h 00FFh
0080h
Short Addressing RAM (zero page)
00FFh 0100h
256 Bytes RAM
017Fh 0180h 013Fh 0140h
16-bit Addressing RAM 16-bit Addressing
Reserved
DFFFh E000h
64 Bytes Stack
017Fh
8K Bytes Program Memory
FFDFh FFE0h
Interrupt & Reset Vectors (see Table 2)
FFFFh
Table 2. Interrupt Vector Map
Vector Address FFE0-FFE1h FFE2-FFE3h FFE4-FFE5h FFE6-FFE7h FFE8-FFE9h FFEA-FF EBh FFEC-FFEDh FFEE-FFEFh FFF0-FF F1h FFF2-FF F3h FFF4-FF F5h FFF6-FF F7h FFF8-FF F9h FFFA-FFFBh FFFC-FF FDh FFFE-FF FFh Description Not Used Not Used Not Used Not Used Not Used TIMER B Interrupt Vector TIMER A Interrupt Vector SPI Interrupt Vector MTC Interrupt Vector 3 (D, O, R & E events) MTC Interrupt Vector 2 (C event) MTC Interrupt Vector 1 (Z event) External Interrupt Vector EI2 (PB0:PB5) External Interrupt Vector EI1 (PA0:PA7) Not Used TRAP (software) Interrupt Vector RESET Vector CPU Interrupt Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt External Interrupt External Interrupt Remarks
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Table 3. Hardware Register Memory Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h to 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h to 0030h 0031h 0032h 0033h 0034h-0035h 0036h-0037h 0038h-0039h 003Ah-003Bh 003Ch-003Dh 003Eh-003Fh 0040h Timer A TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR SPI MISCR SPIDR SPICR SPISR WDGCR WDGSR Port B PBDR PBDDR PBOR Block Register Label PADR PADDR PAOR Register Name Data Register Data Direction Register Option Register Reserved Area (1 byte) Data Register Data Direction Register Option Register Reserved Area (25 bytes) Miscellaneous Register SPI Data I/O Register SPI Control Register SPI Status Register Watchdog Control Register Watchdog Status Register Reserved Area (11 bytes) Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register Reserved Area (1 byte) 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Read Read R/W R/W Read Read Read Read Read Read R/W R/W 00h xxh 0xh 00h 7Fh x0h R/W R/W Read Only R/W Read Only 00h 00h 00h R/W R/W R/W Reset Status 00h 00h 00h Remarks R/W R/W R/W
Port A
WDG
Only Only Only
Only Only Only Only Only Only
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Address 0041h 0042h 0043h 0044h-0045h 0046h-0047h 0048h-0049h 004Ah-004Bh 004Ch-004Dh 004Eh-004Fh 0050h to 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh to 006Fh 0070h 0071h 0072h to 007Fh
Block
Register Label TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR
Register Name Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register Reserved Area (16 bytes)
Reset Status 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h
Remarks R/W R/W Read Read Read R/W R/W Read Read Read Read Read Read R/W R/W
Only Only Only
Timer B
Only Only Only Only Only Only
Motor Control
MCNT MZPRV MZREG MCREG MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MPHST MPAR MPOL
Counter Register Zn-1 Capture Register Zn Capture Register C n+1Compare Register D capture/Compare Register Weight Register Prescaler and Ratio Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Phase State Register Output Parity Register Output Polarity Register Reserved Area (2 bytes)
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADC
ADCDR ADCCSR
Data Register Control/ Status Register Reserved Area (14 bytes)
00h 00h
Read Only R/W
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ST72141
2 Motor Control peripheral overview
The Motor Control (MTC) peripheral can be seen as a Pulse Width Modulator which can be multiplexed on six output channels, and a Back Electromotive Force (BEMF) zero-crossing detector which enables a sensorless control of self commutated Permanent Magnet Direct Current (PMDC) brushless motor. This peripheral is particularly suited to driving synchronous motors and enables the implementation of operating modes like s Commutation step control with motor voltage regulation. s Commutation step control with motor current regulation, i.e. direct torque control. s Sensor or sensorless motor phase commutation control. s BEMF zero-crossing detection with high sensitivity. The integrated phase voltage comparator is directly referred to the full BEMF voltage without any attenuation. So a BEMF voltage down to 200mV can be detected, providing high noise immunity and a selfcommutated operation in a large speed range. s Real time motor winding demagnetisation detection enabling to fine-tune the phase voltage masking time to be applied before BEMF monitoring. s Automatic and programmable delaying between BEMF zero-crossing detection and motor phase commutation. 2.1 MTC peripheral main features
s s
s s s
s
An auto-calibrated prescaler with 16 division steps. One 8-bit by 8-bit multiplier. Phase input multiplexer. Sophisticated output management: - The six output channels can be split in two groups (high side & low side). - The PWM signal can be multiplexed on high, low or both groups, alternatively or simultaneously. - The output polarity is programmable channel by channel. - An output enable bit forces the outputs in HiZ (active low). - An emergency stop pin input (MCES) immediately forces the outputs in HiZ when reset. The MTC peripheral always operates at a 4MHz frequency, equal to fCPU or fCPU/2 depending on the external clock frequency, and not affected by slow mode selection.
2.2 General principle The following example (Figure 6) relates to a six step command sequence for a PMDC brushless motor. The commutation event [Cn] is automatically generated by the MTC peripheral after detecting the zero-crossing of the BEMF induced in the non-exited coil by the rotor. The delay between this event [Zn] and the commutation is computed by the MTC peripheral. The BEMF zero-crossing detection is enabled only after the end of demagnetization event [Dn], also detected (or simulated) by the MTC peripheral. The speed regulation is managed by the microcontroller, by means of an adjustable reference current level (current control), or by the PWM dutycycle adjustment (voltage control). All the detection of [Zn] events is done during a short measurement window while the high side switch is turned off. The high side node (refer to Table 4) is tied to 0V by the free-wheeling diode, and the "zero-crossing" detection is then possible.
s
s
s
Two on-chip analog comparators, one for BEMF zero-crossing detection with an 100mV hysteresis, the other for current regulation or limitation. One of four selectable internal voltage reference values for the hysteresis comparator (0.2V, 0.6V, 1.2V, 2.5V). One central 8-bit timer with two compare registers and two capture features. A "measurement window generator" allowing BEMF zero-crossing detection.
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Figure 6. Example of command sequence for 6-step mode
Step Switch T0 T1 I1 T2 T3 T4 T5 Node A
300V 150V 0
1
2
3
4
5
6
1
2
3
300V
T0 B
T2
T4
I6
I4
I3
A I5
I2
C
T3
T5
T1
B
300V 150V 0 300V 150V 0
C
Note: Control & sampling PWM influence is not represented on these simplified chronograms.
2
300V
3
4
5
150V
superimposed voltage (BEMF induced by rotor)
0V
[D2 ]
[Z2] [C2]
[C4]
[Z 5] [D5] t
Demagnetization
Commutation delay
Wait for BEMF = 0
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Table 4. Step configuration summary
Step Current direction High side active switch Low side active switch Measure done on 1 A(+)/B(-) T0 T5 MCIC 2 A(+)/C(-) T0 T1 MCIB 3 B(+)/C(-) T2 T1 MCIA 4 B(+)/A(-) T2 T3 MCIC 5 C(+)/A(-) T4 T3 MCIB 6 C(+)/B(-) T4 T5 MCIA
Figure 7. Simplified MTC peripheral block diagram (without microcontroller interface) DELAY MANAGER
BEMF ZERO-CROSSING DETECTOR BEMF=0 [Z] DELAY WEIGHT CAPTURE Zn TIMER MCIA MCIB MCIC
Internal VREF DELAY = WEIGHT x Zn =? COMMUTE [C] MCO5 MEASUREMENT WINDOW GENRATOR (I) CURRENT VOLTAGE (V) (I) (V) MODE MCES MCCFI (V) PWM (*) OCP1A (I) MCO4 PHASE MCO3 MCO2 MCO1 MCO0
PWM MANAGER
Note (*) : The PWM signal is generated by Timer A [Z] : Back EMF Zero-crossing event Zn : Time elapsed between two consecutive Z events [C] : Commutation event Cn : Time delayed after Z event to generate C event (I): Current mode (V): Voltage mode
CHANNEL MANAGER
C ext (I)
R ext (V)
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3 MTC Peripheral general description
The MTC peripheral can be split into four main parts as described in the simplified block diagram (Figure 7). - The PWM MANAGER, including a "measurement window generator", a mode selector and current control. - The BEMF ZERO-CROSSING DETECTOR with a comparator and an input multiplexer. - The DELAY MANAGER with an 8 bit timer and an 8x8 bit multiplier. - The CHANNEL MANAGER with the PWM multiplexer, polarity programming capability and emergency HiZ configuration input. 3.1 PWM Manager The PWM manager enables a voltage control or a current control of the motor to be performed via the six output channels. 3.1.1 Voltage Mode In voltage mode, the PWM provided by TimerA is directed to the channel manager. Its duty cycle is adjusted by software according to the needs of the application (speed regulation for example). The current comparator is used for safety purpose as a current limitation, with a limit fixed by means of an internal resistor bridge, adjustable with an external resistor (Rext on OCP1A). 3.1.2 Current Mode In current mode, the PWM output signal is generated by a combination of the "measurement window generator" and the current comparator outputs, and is directed to the channel manager. The "on state" of the resulting PWM starts at the end of the "measurement window" (rising edge), and ends either at the beginning of the next "measurement window" (falling edge), or when the current level in the exited coils reaches the current reference. This current reference is provided to the comparator by the PWM output of TimerA (0.25% resolution), filtered through a RC (integrated resistor and external capacitor Cext on OCP1A). 3.2 Channel manager The channel manager includes a channel state register, a multiplexer with upper and lower channel differentiation, a polarity register and a tri-state output buffer. A pre-load register enables the CPU to asynchronously update the channel configuration for the next step. The multiplexer directs the PWM to the upper channel, the lower channel or both of them alternatively or simultaneously, enabling to choose the most appropriate reference potential when freewheeling the motor in order to improve system efficiency and speed up the demagnetisation phase. The polarity register is used to fit the polarity of the power drivers keeping the same control logic and software. 3.3 BEMF zero-crossing detector This detector is made of: - a phase multiplexer for addressing the non-excited motor winding - an analog comparator referred to a selectable voltage level for zero-crossing detection. This voltage reference can be chosen between four values, depending on the noise level and the voltage supply of the application - a latch to sample the BEMF zero-crossing detection. This block is used for detecting BEMF zero-crossing and end of demagnetization events. The BEMF detections are performed during the "measurement window", when free-wheeling through the low side switches. The zero-crossing sampling frequency is then defined by the "measurement window generator" frequency. 3.4 Delay manager The delay manager computes in real time the delay between the BEMF zero-crossing detection and the next step commutation. It includes an 8 bit timer with two capture, two compare registers and an 8x8 bit multiplier. An auto-updated prescaler always configures the timer in the best accuracy area. Two BEMF zero-crossing consecutive events are memorized by the capture registers. Starting from those values, and using parameters preset by the CPU, the delay manager calculates the value to be loaded in a compare register, which automatically triggers the next commutation. The second compare register is used for end of demagnetization simulation when the event is not detectable ([D2] on the example of Figure 6).
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publicatio n are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)1998 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I 2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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